Topic No. 7 Preferred format: Oral CHIP-SCALE SIMULATION OF RESIDUAL LAYER THICKNESS UNIFORMITY IN THERMAL NANOIMPRINT LITHOGRAPHY: EVALUATING STAMP CAVITY-HEIGHT AND ‘DUMMY-FILL’ SELECTION STRATEGIES

We use chip-scale thermal nanoimprint simulations to show that the addition of non-functional ‘dummy’ features to a realistic integrated-circuit stamp design can substantially improve both residual layer thickness (RLT) uniformity and the completeness of stamp cavity filling at the end of a given nanoimprint process. We also show that although an arbitrarily small average RLT can be obtained if stamp cavities are tall enough not to fill with resist, unfilled cavities do not necessarily guarantee minimal RLT variation — the quantity that is key to controlling critical dimensions of structures that might subsequently be etched using the imprinted pattern as a mask. To help elucidate nanoimprint pattern dependencies, we have used our previously described fast simulation technique, which we have validated experimentally [1, 2], to model imprinting by a silicon stamp whose features are arranged in long, parallel stripes of alternating protrusion density (Fig 1). The stamp’s cavity height, h, is chosen so that complete cavity-filling occurs with an average RLT of one-third the mask regions’ average thickness. For stripe widths, W, up to a few tens of micrometers, the time for cavities to fill completely with resist scales as W. For larger W, stamp deflections enable early cavity filling near the center of lower-density stripes, and filling time falls towards a value that depends on the density contrast, Δρ, between stripes. Meanwhile, the amplitude of any spatial RLT variation decays exponentially with imprint time. With polymeric stamps, which are ~100 times less stiff than silicon, stamp deflections for a given pressure are larger and allow far faster cavity-filling, and RLT variation would likely dominate. We also find (Fig 2) that a reasonable approximation to the cavity-filling time of a pattern may be provided by extracting, for a few values of W, the maximal density difference Δρ between any two abutting W×W regions of the pattern, and summing the times that our model of Fig 1 predicts for all chosen W and their corresponding extracted Δρ. This approach is able to describe the filling times of randomly generated ‘patchwork’ patterns to within a factor of five across two orders of magnitude. Such an estimator of imprint time could be used to drive dummy-fill placement. To investigate the relevance of dummy-fill placement and cavity-height selection in a real design, we have simulated the imprinting of the Metal-1 layout of an integrated circuit, including a large sea of customdesigned logic and a full pad-ring. Feature-area and -perimeter densities have been extracted from the chip’s layout on a 3.75-μm grid. A characteristic feature diameter is inferred for each region of the grid from the extracted densities. Our simulation technique captures both feature size and density dependencies, and so can simulate the initial filling of cavities as well as subsequent homogenization of RLT as resist flows laterally over distances of many micrometers. If cavities are shallow enough to fill with resist during imprinting, setting the pattern density of each region of the grid as close as possible to the chip-average substantially reduces the peak transient range of RLT (Fig 3, case A). Complete cavity filling is also achieved earlier than without the addition of ‘dummy fill’. Meanwhile, if cavities are tall enough never to fill (cases B and C), RLT naturally approaches a much smaller average value. If, however, stamp-average pressure is maintained at the same 5 MPa level as in the cavityfilling case, the peak transient RLT range is much larger. Even reducing the pressure by a factor of 10 results in an RLT range that is less favorable than case A with dummy fill. We conclude that if the etch-selectivity of the resist allows for an appreciable average RLT, uniformity may be best served by filling cavities and employing dummy fill. Word Count: 618